Memory subsystem plays a vital role in embedded systems. Since it' s hard to obtain increasingly capaacty for traditional memory systems, NAND Flash based SSM (solid state memory), especially heterogeneous SSM with RAM (read only memory), is becoming more and more widely used. Corresponding to low speed problem in SSM, cache and parallel technologies are commonly used for optimization. However, it poses a significant challenge to integrate them into a single solution in most appli cations. This article presents a mechanism based on cyclic btfffer and integrates caches with parallel technologies. Cache and Storage modules are connected through a switch-matrix. A unified buffer is introduced to handle errors. Benefiting from dual bus infrastructure,also flexible addressing and scheduling strategies, this approach can largely improve data level parallelism. Verification and empirical experiment results demonstrate the concept with high speed and satisfactory performance. Prototyping system shows the feasibility of the placement layout and routing within circuit board.%存储子系统是嵌入式系统的重要组成部分.由于传统存储系统的设计已经无法满足容量日益增长的需求,固态存储器的应用越来越广泛.针对固态存储系统的存取速率慢的问题,目前常用的优化技术主要有缓存和并行读写技术.然而,在大多数应用和研究中,如何将这两类技术进行融合是目前遇到的一个重大挑战.对此,本文提出一种融合了缓存技术和并行读写技术的基于循环缓冲的新型缓存机制.本方案将缓冲和固态存储模块通过交叉矩阵进行互联,并用专门的缓冲来进行读写过程中的错误处理.理论计算和仿真实验表明该机制能够有效地提升大容量固态存储系统的访问速率.原型系统证明本方案具有直接在电路板布局布线实现的高可行性.
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