A novel four-quadrant CMOS analog multiplier/divider.

摘要

Recently, a number of analog multipliers based on the square-law model of the metal-oxide-silicon (MOS) transistor operating in the saturation region have been presented. This thesis presents a novel four-quadrant complementary metal-oxide-silicon (CMOS) analog multiplier/divider circuit using the 3.3V, 0.18mum CMOS process of Taiwan Semiconductor Manufacturing Company, Ltd (TSMC) based on the square-law model of the MOS transistor. The proposed analog multiplier/divider uses two newly-proposed analog multipliers, a negative feedback path and a common-mode feedback (CMFB) circuit to realize the following transfer function: W = (K2 - K1)*(X2 - X 1)/(Z2 - Z 1) + Y1, where W is the output, K1,2, X1,2 and Z1,2 are differential inputs and Y1 is a DC bias voltage. Spectre(S) simulation results from a chip design show that the 3dB bandwidth of the analog divider is proportional to the magnitude of input signal (Z2 - Z1), and a 3dB bandwidth of 11 MHz is achievable.