Architecting on-chip interconnection network for future many-core chip-multiprocessors.

摘要

The rapid process scaling trend of the silicon industry has provided the resources to concurrently execute multiple instruction sequences on the same chip, a capability conventionally only available with bulky and expensive parallel computers and distributed multiprocessors. A range of chips have emerged with simultaneous multi-tasking capability, and received a well-known name "chip-multiprocessors" (CMP) which emphasizes their connections with the much bulkier predecessors, conventional distributed multiprocessors. As possibly the only cost-effective approach to keep Moore's law alive, CMP architectures have received tremendous research and developments efforts further boosting their multi-tasking capabilities (increased number of computing units, improved shared cache architecture, better scheduling and power management, etc.). In particular, as a crucial part of the on-chip system, on-chip interconnection network has become a heated field that draws great research interests and yet presents numerous challenges.;The most critical challenges facing on-chip interconnection network researches are the large design space and the disparaging requirements imposed by different applications. Lacking standards and demanding high performance, most proposed on-chip interconnection network architectures adopt technologies transferred from off-chip interconnection networks developed for conventional multiprocessors. However, the constraints imposed by the on-chip environment and the even stringent demand of low latency and high throughput makes the on-chip interconnection network essentially different from the off-chip counterparts, and elicits innovative approaches to efficient on-chip network architectures.;In this thesis an extensive view of researches on on-chip interconnection networks is presented. In the first two chapters, preliminary knowledge about and recent work on on-chip interconnection network is reviewed. In the following chapters, our work on exploring and improving the design of on-chip interconnection networks is presented. Particularly, in Chapter 4 novel architectures that provide quality-of-service at the interconnect-level are presented, and in Chapter 3 emerging interconnect techniques are leveraged to further improve the efficiency of on-chip interconnection networks. The final chapter highlights the observations and the findings obtained from foregoing chapters, as well as discusses open issues in this field.