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A quad-core 15GHz BiCMOS VCO with −124dBc/Hz phase noise at 1MHz offset, −189dBc/Hz FOM, and robust to multimode concurrent oscillations

机译:具有1MHz偏移时的−124dBc / Hz相位噪声,−189dBc / Hz FOM的四核15GHz BiCMOS VCO,对多模并发振荡具有鲁棒性

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The relentless development of next-generation communication and radar systems sets increasingly stringent requirements on the spectral purity of local oscillators. Decreasing phase noise is crucial to support efficient modulation formats with large symbol constellations, as well as to enable innovative radar applications, e.g., anti-collision, gesture recognition, and medical imaging. To minimize phase noise, bipolar transistors offer some advantages over ultra-scaled CMOS: higher supply voltage (thus larger oscillation amplitudes), lower 1/f noise, higher-Q passives (due to higher resistivity substrate and, possibly, thicker metals), and higher fT, fmaxfor a given technology node, which results in a cost advantage for a variety of medium-volume applications (e.g., infrastructure transceivers). For a given supply voltage, a tank showing a smaller resistance at resonance yields lower phase noise. As a result, the minimum phase noise achievable by a single voltage-controlled oscillator (VCO) is ultimately bounded by the smaller realizable inductor displaying the highest Q. To achieve significantly lower phase noise levels, bilaterally coupling N oscillators [1-3] is a viable option. However, to fully preserve the 10log(N) phase-noise advantage, while avoiding undesired multi-tone concurrent oscillations, the coupling network must be carefully designed. This work presents a quad-core bipolar VCO achieving phase noise as low as -124dBc/Hz at 1MHz offset from the 15GHz carrier, -189dBc/Hz figure-of-merit (FOM), and 16% tuning range. Insights are given into the design of the resistive network employed to couple the four oscillators, a key element in achieving the reported performance.
机译:下一代通信和雷达系统的不懈发展对本地振荡器的频谱纯度提出了越来越严格的要求。降低相位噪声对于支持具有大符号星座的高效调制格式以及实现创新的雷达应用(例如防撞,手势识别和医学成像)至关重要。为了将相位噪声降至最低,双极型晶体管比超大规模CMOS具有一些优势:更高的电源电压(因此振荡幅度更大),更低的1 / f噪声,更高的Q无源(由于更高的衬底电阻率以及可能更厚的金属),和更高的f T , F max 对于给定的技术节点而言,这对于各种中等容量的应用(例如,基础设施收发器)产生了成本优势。对于给定的电源电压,在谐振时显示较小电阻的储能电路会产生较低的相位噪声。结果,单个压控振荡器(VCO)所能达到的最小相位噪声最终受到显示最高Q的较小的可实现电感器的限制。为实现显着较低的相位噪声水平,双向耦合N个振荡器[1-3]为一个可行的选择。但是,为了完全保留10log(N)的相位噪声优势,同时避免了不希望的多音并发振荡,必须精心设计耦合网络。这项工作提出了一种四核双极VCO,在距15GHz载波1MHz的偏移处,其相位噪声可低至-124dBc / Hz,-189dBc / Hz品质因数(FOM),以及16%的调谐范围。深入了解了用于耦合四个振荡器的电阻网络的设计,这是实现所报告性能的关键因素。

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