首页> 外文会议>IEEE International Solid-State Circuits Conference >A quad-core 15GHz BiCMOS VCO with ?124dBc/Hz phase noise at 1MHz offset, ?189dBc/Hz FOM, and robust to multimode concurrent oscillations
【24h】

A quad-core 15GHz BiCMOS VCO with ?124dBc/Hz phase noise at 1MHz offset, ?189dBc/Hz FOM, and robust to multimode concurrent oscillations

机译:四核15GHz BICMOS VCO,具有1MHz偏移量的124dBC / Hz相位噪声,?189dBc / Hz FOM,以及多模并发振荡的强大

获取原文

摘要

The relentless development of next-generation communication and radar systems sets increasingly stringent requirements on the spectral purity of local oscillators. Decreasing phase noise is crucial to support efficient modulation formats with large symbol constellations, as well as to enable innovative radar applications, e.g., anti-collision, gesture recognition, and medical imaging. To minimize phase noise, bipolar transistors offer some advantages over ultra-scaled CMOS: higher supply voltage (thus larger oscillation amplitudes), lower 1/f noise, higher-Q passives (due to higher resistivity substrate and, possibly, thicker metals), and higher fT, fmaxfor a given technology node, which results in a cost advantage for a variety of medium-volume applications (e.g., infrastructure transceivers). For a given supply voltage, a tank showing a smaller resistance at resonance yields lower phase noise. As a result, the minimum phase noise achievable by a single voltage-controlled oscillator (VCO) is ultimately bounded by the smaller realizable inductor displaying the highest Q. To achieve significantly lower phase noise levels, bilaterally coupling N oscillators [1-3] is a viable option. However, to fully preserve the 10log(N) phase-noise advantage, while avoiding undesired multi-tone concurrent oscillations, the coupling network must be carefully designed. This work presents a quad-core bipolar VCO achieving phase noise as low as -124dBc/Hz at 1MHz offset from the 15GHz carrier, -189dBc/Hz figure-of-merit (FOM), and 16% tuning range. Insights are given into the design of the resistive network employed to couple the four oscillators, a key element in achieving the reported performance.
机译:下一代通信和雷达系统的无情地发展对本地振荡器的频谱纯度来说越来越严格。降低相位噪声对于支持具有大符号星座的有效调制格式,以及实现创新的雷达应用,例如,防碰撞,手势识别和医学成像。为了最小化相位噪声,双极晶体管通过超缩放的CMOS提供一些优点:较高的电源电压(因此较大的振荡幅度),低1 / F噪声,更高Q的峰值(由于较高的电阻率底物,并且可能更厚的金属),和更高的F. t , F max 对于给定的技术节点,这导致各种中卷应用(例如,基础设施收发器)的成本优势。对于给定的电源电压,表示谐振处的较小电阻的罐产生较低的相位噪声。结果,通过单个电压控制振荡器(VCO)可实现的最小相位噪声最终由显示最高Q的较小可变电感器。为了实现显着降低的相位噪声水平,双侧耦合N振荡器[1-3]是一个可行的选择。然而,为了完全保留10Log(n)相位噪声优势,同时避免不需要的多音并行振荡,必须仔细设计耦合网络。这项工作介绍了从15GHz载波,-189dBc / Hz的1MHz偏移量低至-124dBc / hz的四核双极VCO,从15GHz载波,-189dBc / hz of lemit(fom)和16 %调谐范围。洞察中的电阻网络设计用于将四个振荡器结合的电阻网络,是实现报告的性能的关键因素。

著录项

相似文献

  • 外文文献
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号