首页> 外文会议>IEEE International Solid- State Circuits Conference >A high-efficiency and fast-transient digital-low-dropout regulator with the burst mode corresponding to the power-saving modes of DC-DC switching converters
【24h】

A high-efficiency and fast-transient digital-low-dropout regulator with the burst mode corresponding to the power-saving modes of DC-DC switching converters

机译:一种高效且瞬态的数字低压降稳压器,其突发模式对应于DC-DC开关转换器的节能模式

获取原文

摘要

Integrated power management (PM) in a system-on-a-chip (SoC) includes a high-efficiency DC-DC switching regulator (SWR) for a high conversion ratio and multiple cascaded digital-low-dropout (DLDO) regulators for post regulation to different functional blocks. Efficient power-saving modes in the SWRs improve the light-load efficiency effectively, e.g. burst mode, skip mode, pulse frequency mode (PFM), and diode emulation mode (DEM) in the constant on-time (COT). Unfortunately, a cascaded DLDO consumes significant power to suppress a large voltage ripple DVSWR from the SWR, even using recent DLDO techniques [1-6], illustrated on the left of Fig. 18.8.1. Overall, the light-load efficiency of the PM seriously decreases. A DLDo with barrel-shifter-based control [1] induces large voltage ripple due to the limiting cycle oscillation (LCO), and the DLDO with freeze mode [2] for power reduction is exposed to large voltage ripples from the SWRs (in power saving modes). The large voltage ripples result in the DLDO frequently switching between the normal and freeze modes and consuming power. The recursive all-digital LDO (RLDO) [3] abruptly changes its control code Q[6:0] due to oscillations between hybrid proportional-derivative successive-approximation recursive (PD-SAR) and pulse width modulation (PWM) duty control, while aVSWR is larger than the pre-defined hysteretic window. In power saving modes, the obvious disadvantage is that state-of-the-art DLDO designs cause extra switching loss and induce large output voltage ripple aVOUT due to large aVSWR. Thus, this paper proposes a DLDO employing a burst mode technique (BMT) to reduce the DVOUT, thereby enhancing the overall light-load efficiency corresponding to the power saving modes in SWRs. The proposed non-linear switch control (NLSC) technique reduces both the number of on/off power switches and varies the switching frequency corresponding to the aVSWR. Moreover, the proposed transient enhance (TE) technique improves transient performance when the DLDO leaves burst mode.
机译:片上系统(SoC)中的集成电源管理(PM)包括用于高转换率的高效DC-DC开关稳压器(SWR)和用于后置的多个级联数字低压降(DLDO)稳压器调节到不同的功能块。 SWR中的高效节能模式可有效提高轻载效率,例如恒定导通时间(COT)中的突发模式,跳过模式,脉冲频率模式(PFM)和二极管仿真模式(DEM)。不幸的是,级联的DLDO甚至要使用最新的DLDO技术[1-6],如图18.8.1左侧所示,也要消耗大量功率来抑制来自SWR的大电压纹波DV SWR 。总体而言,PM的轻载效率严重下降。具有基于桶形移位器的控制的DLDo [1]由于极限循环振荡(LCO)会引起较大的电压纹波,而具有降压模式的DLDO [2]会降低功耗,从而受到来自SWR的较大电压纹波的影响(在电源中保存模式)。较大的电压纹波会导致DLDO频繁在正常模式和冻结模式之间切换,并消耗功率。由于混合比例微分逐次逼近递归(PD-SAR)和脉宽调制(PWM)占空比控制之间的振荡,因此,递归全数字LDO(RLDO)[3]突然更改了其控制代码Q [6:0],而aV SWR 大于预定义的滞后窗口。在省电模式下,明显的缺点是,最新的DLDO设计会导致额外的开关损耗,并且由于较大的aV SWR 而导致较大的输出电压纹波aV OUT 。因此,本文提出了一种采用突发模式技术(BMT)来降低DV OUT 的DLDO,从而提高了与SWR中的节能模式相对应的总体轻载效率。提出的非线性开关控制(NLSC)技术减少了开/关电源开关的数量,并改变了与aV SWR 相对应的开关频率。此外,当DLDO离开突发模式时,提出的瞬态增强(TE)技术可改善瞬态性能。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号