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DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy

机译:DEW:具有FIFO替换策略的嵌入式处理器的快速1级高速缓存模拟方法

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Increasing the speed of cache simulation to obtain hit/miss rates enables performance estimation, cache exploration for embedded systems and energy estimation. Previously, such simulations, particularly exact approaches, have been exclusively for caches which utilize the least recently used (LRU) replacement policy. In this paper, we propose a new, fast and exact cache simulation method for the First In First Out(FIFO) replacement policy. This method, called DEW, is able to simulate multiple level 1 cache configurations (different set sizes, associativities, and block sizes) with FIFO replacement policy. DEW utilizes a binomial tree based representation of cache configurations and a novel searching method to speed up simulation over single cache simulators like Dinero IV. Depending on different cache block sizes and benchmark applications, DEW operates around 8 to 40 times faster than Dinero IV. Dinero IV compares 2.17 to 19.42 times more cache ways than DEW to determine accurate miss rates.
机译:提高高速缓存仿真速度以获得命中率/未命中率,可以进行性能评估,嵌入式系统的高速缓存探索和能量估算。以前,此类仿真(尤其是精确的方法)专门用于利用最近最少使用(LRU)替换策略的缓存。在本文中,我们为先进先出(FIFO)替换策略提出了一种新的,快速且精确的缓存模拟方法。这种称为DEW的方法可以使用FIFO替换策略来模拟多个1级缓存配置(不同的集合大小,关联性和块大小)。 DEW利用基于二叉树的缓存配置表示和一种新颖的搜索方法来加快像Dinero IV这样的单个缓存模拟器的仿真速度。根据不同的缓存块大小和基准应用程序,DEW的运行速度比Dinero IV快8到40倍。 Dinero IV的缓存方式比DEW多出2.17至19.42倍,以确定准确的未命中率。

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