An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation

摘要

A wide tuning range LO generation architecture for software defined radio is presented. A dual VCO approach followed by a programmable divider chain based on high-speed dynamic CMOS latches provides full rail-to-rail operation with low power consumption. The 1.2 V 90 nm CMOS implementation achieves a VCO tuning range between 6 to 13.6 GHz for a power consumption between 3.5 to 13.4 mW and phase noise figure of merit of 182 dBc/Hz measured at 3 MHz offset from a 12 GHz carrier. The VCO-multiplexer and divider chain consumes between 5.9 to 8.1 mW for this frequency range.