JEDEC固态技术协会_国内外标准网文献检索下载

1.[标准] External Visual

外部视觉

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD22-B101D

发布时间：
2022-04-01

中标分类：
-

国标分类：
-

实施时间：

摘要： External visual inspection is an examination of the external surfaces, construction, marking, and workmanship of a finished packaged device. External visual is a noninvasive and nondestructive test. It is functional for qualification, quality monitoring, and lot acceptance.This test method is applicable to:- finished packaged devices only (hereafter referred to as 'devices');NOTE Devices sampled for external visual inspection must be considered physically representative of the as-shipped product.- all solid-state device package types/styles;- devices having attachments as shipped (see clause 3 for definition).This test method is not applicable to:- customer-processed devices (see clause 3 for definition);- piece parts incoming to a device assembly operation, or to sub-assemblies in a manufacturing line (WIP);- the carrier, dry bag, packing, or container used to ship devices;- the orientation or loading aspects of devices in carriers, (applicable to the device only);- the internal, non-viewable features of a device.This test method does not apply to or require any inspection, measurement, or analysis other than the procedure described in clause 5.This test method does not preclude the use of specialized tools or equipment to inspect or measure devices for conformance to physical specifications.
2.[标准] DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Specification

DDR5减载（LRDIMM）和注册双列直插存储器模块（RDIMM）通用规范

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD305

发布时间：
2022-01-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This standard defines the electrical and mechanical requirements for 288-pin, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM) and Load Reduced (LRDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These 288-pin Registered and Load Reduced DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments. Item 2273.07.
3.[标准] TS5111, TS5110 Serial Bus Thermal Sensor Device Standard

TS5111、TS5110串行总线热传感器设备标准

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
历史

标准号：
JEDEC JESD302-1

发布时间：
2022-01-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS5111 and TS5110 refers to the device specified by this document.The purpose is to provide a standard for the TS5 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.Unless otherwise noted in the document, any illegal operation is not allowed and device operation is not guaranteed.
4.[标准] DDR5 RDIMM Standard Annex B

DDR5 RDIMM标准附录B

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD305-R4-RCB Version 1.0

发布时间：
2022-04-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This standard, JESD305-R4-RCB, DDR5 Registered Dual Inline Memory Module with 4-bit ECC (EC4 RDIMM) Raw Card B Annex, defines the design detail of x4, 2 Package Ranks DDR5 RDIMM with 4-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Standard.
5.[标准] Recommended ESD-CDM Target Levels

建议的ESD-CDM目标水平

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JEP157A

发布时间：
2022-04-01

中标分类：
-

国标分类：
-

实施时间：

摘要： The intent of this report is to document and provide critical information to assess and make decisions on safe CDM ESD level requirements. The scope of this document is to provide this information to quality organizations in both semiconductor companies and their IC customers.
6.[标准] DDR5 RDIMM Standard Annex D

DDR5 RDIMM标准附录D

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD305-R8-RCD Version 1.0

发布时间：
2022-04-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This standard, JESD305-R8-RCD, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card D Annex, defines the design detail of x8, 1 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Standard.
7.[标准] Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Electronic Devices

电子设备用有机材料中水分扩散率和水溶性测量的试验方法

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD22-A120C

发布时间：
2022-01-01

中标分类：
-

国标分类：
-

实施时间：

摘要： The purpose of this test method is to provide a means for determining the moisture sorption properties of organic materials used in the packaging of electronic devices.This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow.
8.[标准] High Bandwidth Memory (HBM) DRAM (HBM1, HBM2)

高带宽存储器（HBM）DRAM（HBM1、HBM2）

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD235D

发布时间：
2021-02-01

中标分类：
-

国标分类：
-

实施时间：

摘要： The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L.
9.[标准] Low Power Double Data Rate 5/5X (LPDDR5/LPDDR5X)

低功耗双数据速率5/5X（LPDDR5/LPDDR5X）

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
历史

标准号：
JEDEC JESD209-5B

发布时间：
2021-06-01

中标分类：
-

国标分类：
-

实施时间：
10.[标准] Serial Interface for Data Converters

数据转换器的串行接口

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD204C.1

发布时间：
2021-12-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This specification describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative sections are included to clarify and exemplify the specification.
11.[标准] Graphics Double Data Rate 6 (GDDR6) 5GRAM Standard

图形双数据速率6（GDDR6）5GRAM标准

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD250C

发布时间：
2021-02-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Item 1836.99E.
12.[标准] Backup Energy Module Standard for NVDIMM Memory Devices (BEM)

NVDIMM存储设备（BEM）的备用能源模块标准

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD315

发布时间：
2021-12-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This standard defines the functional requirements of Backup Energy Module (BEM), henceforth referred to as BEM in this standard. This module shall be used to provide backup power to the Industry Defined Storage Array Controller Cards and NVDIMM-n as applicable. All standards are applicable under all operating conditions unless otherwise stated.
13.[标准] Replay Protected Monotonic Counter (RPMC) For Serial Flash Devices

用于串行闪存设备的重放保护单调计数器（RPMC）

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD260

发布时间：
2021-04-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This document provides the requirements for an additional block called as Replay Protection Monotonic Counter. (RPMC) Replay Protection provides a building block towards providing additional security. This block requires modifications in both a Serial Flash device and Serial Flash Controller. The standard defines new commands for Replay Protected Monotonic Counter operations. A device that supports RPMC can support these new commands as defined in this standard.
14.[标准] Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0

1.0版横向GaN功率转换装置数据表中规定瞬态关态耐压稳健性指示器的指南

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JEP186

发布时间：
2021-12-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained.
15.[标准] Enclosure Form Factor For SSD Devices, Version 1.0

SSD设备的外壳形状系数 1.0版

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD253

发布时间：
2021-02-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This document specifies the enclosure form factor which can be used with various type of SSD devices: outline of the top and bottom enclosure, three screw holes to mount the enclosure on the system, and two clamping holes in the top enclosure to lock to the connector. Item 318.06.
16.[标准] Guidelines for Representing Switching Losses of SIC Mosfets in Datasheets

在数据表中表示SIC MOSFET开关损耗的指南

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JEP187

发布时间：
2021-12-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets.
17.[标准] Electrostatic Discharge (ESD) Sensitivity Testing - Reporting ESD Withstand Levels on Datasheets

静电放电（ESD）敏感性试验-在数据表上报告ESD耐受水平

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JEP178

发布时间：
2021-04-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries. Standardized ESD stress test methods have been developed to evaluate the relative sensitivity of devices. Although these methods are available, the results of the testing are not always provided by the suppliers, especially charged device model (CDM) levels. The document provides a standardized template which includes a minimum information set and gives guidelines for expanded individual pin information when needed. The document should improve the availability and usefulness of reported ESD data.
18.[标准] Semiconductor Wafer and Die Backside External Visual Inspection

半导体晶圆和芯片背面外部目视检查

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD22-B118A

发布时间：
2021-11-01

中标分类：
-

国标分类：
-

实施时间：

摘要： Semiconductor wafer and die backside external visual inspection is an examination of the external non-active surface area (hereafter called backside) of processed semiconductor wafers or die. This inspection method is for product semiconductor wafers and dice prior to assembly. This test method defines the requirements to execute a standardized external visual inspection and is a non-invasive and non-destructive examination that can be used for qualification, quality monitoring, and lot acceptance. Alternate methods of inspection or techniques that provide assurance to Clause 6 elements are acceptable (e.g., functional testing, automated inspection equipment, in-line manufacturing operations, etc.).This test method is applicable to:- Backside inspection of semiconductor wafers and die. Wafers and die sampled for external visual inspection must be representative of final product.This test method does not apply to or require any inspection, measurement, or analysis other than the procedure described in clause 5.0. Recommended tools and equipment for this test method are presented in clause 4.0; use of substitute tools or equipment to perform this test method is acceptable provided correlated results are obtained.
19.[标准] Cycled Temperature Humidity-Bias with Surface Condensation Life Test

表面冷凝寿命试验循环温湿度偏差

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
现行

标准号：
JEDEC JESD22-A100E

发布时间：
2020-11-01

中标分类：
-

国标分类：
-

实施时间：

摘要： The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. The Cycled Temperature-Humidity-Bias Life Test is typically performed on cavity packages (e.g., MQUADs, lidded ceramic pin grid arrays, etc.) as an alternative to JESD22-A101 or JESD22-A110.
20.[标准] Temperature Cycling

温度循环

发布单位：
美国-JEDEC固态技术协会(US-JEDECJEDECST)

标准状态：
历史

标准号：
JEDEC JESD22-A104F

发布时间：
2020-11-01

中标分类：
-

国标分类：
-

实施时间：

摘要： This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling. This standard applies to single-, dual- and triple-chamber temperature cycling and covers component and solder interconnection testing. It should be noted that this standard does not cover or apply to thermal shock chambers. This test is conducted to determine the ability of components and solder interconnects to withstand mechanical stresses induced by alternating high- and low-temperature extremes. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses.