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Microprocessor with Multistep-Ahead Branch Predictor
Microprocessor with Multistep-Ahead Branch Predictor
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机译:微处理器具有多级前部分支预测因子
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摘要
A microprocessor with a multistep-ahead branch predictor is shown. The branch predictor is coupled to an instruction cache and has an N-stage pipelined architecture, which is configured to perform branch prediction to control the instruction fetching of the instruction cache. The branch predictor performs branch prediction for (N-1) instruction-address blocks in parallel, wherein the (N-1) instruction-address blocks include a starting instruction-address block and (N-2) subsequent instruction-address blocks. The branch predictor is thereby ahead of branch prediction of the starting instruction-address block. The branch predictor stores reference information about branch prediction in at least one memory and performs a parallel search of the memory for the branch prediction of the (N-1) instruction-address blocks.
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