PARITY GENERATION CIRCUITS FOR A PLURALITY OF ERROR CORRECTION LEVELS, MEMORY CONTROLLERS, AND MEMORY MODULES INCLUDING THE PARITY GENERATION CIRCUITS

摘要

A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.