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Control circuit for integrated circuits, for example for bistable multivibrators

机译:集成电路控制电路,例如双稳态多谐振荡器

摘要

1,091,713. Transistor gating circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 25, 1966 [June 21, 1965], No. 23343/66. Heading H3T. A gating circuit comprises a transistor having its base connected through a resistance to a source of gating pulses and through a capacitor to earth or other fixed potential, the emitter being connected to a source of set pulses. Two such gating transistors 30 and 32, Fig. 1, may have their collectors connected to the inputs of a bi-stable circuit 10, 12, as described in Specification 1,090,709, and the input capacitors 34, 36 serve to store a charge due to the gating pulse so that reliable operation is obtained at switch conditioning times of about 10 nanoseconds. The bases of the gating transistors may be connected by diodes 42, 44 to the collectors of output transistors 14, 16 of the bi-stable circuit to avoid ill effects caused by overshoot of the gating pulse. In a modification, Fig. 2 (not shown), the capacitors (70, 72) of the gating transistors (66, 68) are shunted by transistors (74, 76) having their bases connected to the output terminals (78, 80) of the bi-stable circuit so that the capacitor of the unwanted gate is discharged.
机译:1,091,713。晶体管选通电路。国际商业机器公司。 1966年5月25日[1965年6月21日],编号23343/66。标题H3T。选通电路包括晶体管,该晶体管的基极通过电阻连接到选通脉冲源,并通过电容器连接到大地或其他固定电位,发射极连接到置位脉冲源。如图1 090709所述,图1中的两个这种门控晶体管30和32的集电极可以连接到双稳态电路10、12的输入,并且输入电容器34、36用于存储电荷。选通脉冲,以便在约10纳秒的开关调节时间获得可靠的操作。选通晶体管的基极可以通过二极管42、44连接到双稳态电路的输出晶体管14、16的集电极,以避免由选通脉冲的过冲引起的不良影响。在图2的变型中(未示出),选通晶体管(66、68)的电容器(70、72)被其基极连接到输出端子(78、80)的晶体管(74、76)分流。这样就使双稳态电路的输出端放电,从而使不需要的栅极的电容器放电。

著录项

  • 公开/公告号DE1286094B

    专利类型

  • 公开/公告日1969-01-02

    原文格式PDF

  • 申请/专利权人 IBM;

    申请/专利号DE1966I031108

  • 发明设计人 ROY HARPER LEONARD;

    申请日1966-06-21

  • 分类号H03K3/012;

  • 国家 DE

  • 入库时间 2022-08-23 12:28:24

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