1461245 Memory system HAWKER SIDDELEY DYNAMICS Ltd 21 Feb 1974 [28 Jan 1973] 44762/72 Heading G4A A memory system includes a memory unit interfaced with a first level bus 10, the unit comprising a plurality of sub-units interfaced with a second level bus 16 within the unit, each sub-unit comprising a plurality of blocks 14 interfaced with a third level bus 28 within the sub-unit. The memory may be formed by large scale integrated circuits, each block 14 consisting of two sub-blocks each of two 32 word read/write or read only memory chips. Each chip contains a number of access control registers including a status register, process and block registers. The status register may contain memory protection data limiting access to the chip to read or write only or data preventing the chip responding to accesses to enable the chip to function as a replacement when a different chip becomes faulty. The process and block register contents are compared with the high ordered part of a virtual address, agreement causing the remaining low ordered part of the address to be decoded to select a stored word. The control register contents may be modified, e.g. to reflect data relocation in a virtual memory or to replace a faulty chip, by the operating system software of a data processor in a so called "real access". A "real address" is supplied, over the same or different buses than a virtual address, to the appropriate block by the bus interfaces, and is compared in the selected block with a hard wired address to select the appropriate control register whose contents are modified as appropriate. The interfaces have means for isolating the various levels in the memory, i.e. a whole unit, a sub-unit, or a block, from the appropriate bus in response to faults. Two or more buses may be provided at each level to produce a multi-access port memory.
展开▼
