Transfer of digital data between non-synchronised networks - uses digital circuits for phase control

摘要

Data is transferred between two networks through an 'elastic' memory (EM) such as an n-stage shift register, with n typically 8, into which data is fed synchronously with one network, and from which data is read synchronously with the other. The read and write switching is controlled by n-dividers (D1, D2). The divider outputs are compared in a digital comparator, the output of which feeds via logical gates (P1, P2) a counter (L), such that if the read pulse precedes the write and total is increased by a fixed amount (typically 1) and vice versa. Resetting of the counter may be at regular intervals, when the total is a measure of the phase difference, or after the total exceeds a predetermined value, equivalent to an integrated phase shift. Information transfer is modified in a standard manner if the phase shift is excessive.