Pulse regenerator for slow frequency divider - has flip-flop driven by clock pulses and by divider gated output

摘要

The pulse regenerator, for a synchronised slow divider output pulses, produces rectangular pulses from the divider output in synchronisation with the clock pulses and displaced w.r.t. the divider output by a constant time internal determined by the clock pulses. The clock pulses and the divider output are applied to a sate two inputs. A flip-flop is connected to the gate output and to the clock pulses directly and is driven from one state to the other by these two sets of pulses.