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Muting arrangement for AM synchronous detector using a PLL circuit
Muting arrangement for AM synchronous detector using a PLL circuit
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机译:使用PLL电路的AM同步检波器的静音装置
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摘要
The output voltage of an AM synchronous detector is compared with a reference potential level by a voltage comparator. A muting device connected with the output of the detector is controlled by a control circuit connected with the comparator. Through this control circuit, the detector output is immediately muted when the detector output level falls below the reference potential level, and the muting of the detector output is removed after a predetermined retardation when the detector output level exceeds the reference potential level.
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