High density multilayered semiconductor network - avoids etching errors and damage and minimises tolerance requirements by careful choice of components

摘要

A high density semiconductor and conducting layer matrix (1) is used, where interconnections are made between overlying layers. The design minimises problems of fabricating such devices and allows positional tolerances and engraving times to be reduced during the various masking operations. Undercutting and general damage to the various conducting layers is avoided by choice of suitable material dimensions and the use of etching resistant materials such that layers of silicon and silicon nitride overlap each other. Isolating materials used are silicon oxide and silicon nitride alternating with layers of an aluminium-silicon alloy and a titanium-tungsten alloy, the overlying layer being aluminium.