A standby system to ensure that the contents of a volatile random access memory (RAM) are protected during a mains power supply failure, includes a facility for protection against disturbance pulses. A comparator generates an output if the supply falls below a specified level. A decouplic stage inhibits the RAM write input and an alternate supply maintains the contents. When power returns a timing stage only outputs once it is certain that it is not merely a transient surge. A switching stage removes the inhibitor to the write input and a start pulse is generated.
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