Method and arrangement for securing important information in memory units with optional access, particularly for control bits in buffer memories acting as cache memories in a data processing system

摘要

To raise the functional security of small quantities of information (control bits V, W, S or C) which are protected only by one parity bit (P), with a limited number of permitted bit combinations (K1 to K5) for the secured information including the parity bit (P), the error combinations (a to h) which can be derived from the individual bit combinations are divided into at least two groups. One group (a, b, g, h) allows the operation which depends on the information to continue in spite of a recognised parity error (PERR). The other group indicates that the operation which has been started must be aborted. By additional testing (using VN1) of the information (STB) which has been read, for the presence of an error combination which is assigned to one group or the other, the continuation of the operation which has been started is controlled (using SEG). Reduction of error combinations which are not unambiguously assigned to a group by modification of at least one of the information bits (e.g. S), following linkage with other information bits (e.g. V). Additional double error monitoring (DERR) by testing for unpermitted bit combinations (using VN2). 100% recognition of single errors for cache memories (C-SP) (with three control bits) which operate according to the "copy-back" procedure. IMAGE