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Method of making a heterojunction bipolar transistor with SIPOS
Method of making a heterojunction bipolar transistor with SIPOS
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机译:用SIPOs制造异质结双极晶体管的方法
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摘要
A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.
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