PURPOSE:To pick up a signal with constant phase and changing amplitude, by frequency-dividing a clock signal, taking almost the center time of a frequency output as the pulse center, changing the pulse width with a control signal and passing through the pulse to a logical circuit and an LPF. CONSTITUTION:A clock input signal 1 is applied to a 4-bit binary counter A and an inverter E. An MSB output of the counter A outputs 1/16 frequency dividing waveform of the clock frequency at a terminal 2 via an LPFF1 and is applied to an AND gate C7, and another output of the counter is applied to a decoder B. Output terminals 1-7 of the decoder B are connected to AND gates C1-C6 and an OR gate D, and control signal terminals X, Y, and Z are connected to the gate D via a prescribed gate out of the gates C1-C6. The output of the gate D is applied to an AND gate C8 together with the output of the inverter E via a gate C7. The output of the gate C8 is outputted to a terminal 3 via a monostable multivibrator H and an LPFF2. A control signal produces a signal with constant phase and changing amplitude at the terminal 3.