首页> 外国专利> CIRCUIT FOR CHECKING BIT ERRORS IN A RECEIVED BCH CODE SUCCESSION BY THE USE OF PRIMITIVE AND NON-PRIMITIVE POLYNOMIALS

CIRCUIT FOR CHECKING BIT ERRORS IN A RECEIVED BCH CODE SUCCESSION BY THE USE OF PRIMITIVE AND NON-PRIMITIVE POLYNOMIALS

机译:通过使用本原和非本原多项式来检查接收的BCH代码成功中的位错误的电路

摘要

PURPOSE:To reduce considerably the capacity of an ROM and to improve a decoder, by using the quotient remainder of a primitive polynomial as the address information of the ROM and then comparing the output of the ROM with the quotient remainder of another polynomial. CONSTITUTION:A feedback register 5 divides a receiving data with a polynomial having a primitive root of a polynomial g1(x) of a BCH (Bose-Chaudhuri-Hocquenghem) code and delivers the quotient remainder. While a feedback register 6 divides the receiving data with the 2nd polynomial containing the factors other than those contained at least in the 1st polynomial among the factors of a grown polynomial g3(x) of the BCH code and delivers the quotient remainder. The quotient remainder, i.e., the output of the register 5 is used as an address input for an ROM3. Then the coincidence is detected by a coincidence detecting circuit 7 between the output of the ROM3 and the quotient remainder, i.e., the output of the register 6.
机译:目的:通过使用原始多项式的商余数作为ROM的地址信息,然后将ROM的输出与另一个多项式的商余数进行比较,以大大减少ROM的容量并改进解码器。构成:反馈寄存器5将接收数据与具有BCH(Bose-Chaudhuri-Hocquenghem)码的多项式g1(x)的本底根的多项式相除,并传递商余数。反馈寄存器6在BCH码的增长多项式g3(x)的因数中,将接收数据与第二多项式相除,该第二多项式包含至少不包含在第一多项式中的因数,并传递商余数。商的余数,即寄存器5的输出用作ROM3的地址输入。然后,由一致性检测电路7在ROM3的输出和商余数即寄存器6的输出之间检测一致性。

著录项

  • 公开/公告号SG7991G

    专利类型

  • 公开/公告日1991-04-05

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号SG19910000079

  • 发明设计人

    申请日1991-02-18

  • 分类号G06F11/10;

  • 国家 SG

  • 入库时间 2022-08-22 05:57:18

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