PURPOSE:To reduce the circuit scale of the advanced start priority circuit and to prevent delay time from an input to an output from being increased by generating the output of a specified code when the input of the specified code is applied, holding the state of the output and executing reset according to the state of outputting the specified code for any other data holding means. CONSTITUTION:When a code '1' is applied as a reset signal XRESET and an input data DI1, is turned to the code '1', the '1' is outputted to an output terminal Q of a flip-flop 101 with the rising of a clock signal CK, the output data DI1 is turned to the code '1' and held, and a code '0' is outputted to an inverted output terminal XQ. By outputting the code '0' to the inverted output XR of the flip-flop 101, the output of a gate 202 is turned to the code '0' and therefore, a flip-flop 102, is turned to a reset state. Thus, even when the code '1' is applied to an input data DI2, of the flip-flop 102, the flip-flop 102, cannot be set.
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