ONE BIT ADDER OF FIVE INPUTS/THREE OUTPUTS

摘要

PURPOSE:To improve operation speed by reducing the delay of a critical path. CONSTITUTION:An OR gate constitutes a first OR circuit (a), a NAND gate a first AND circuit (b), a NAND gate 23 a third AND circuit (e), an OR gate 24 a second OR circuit (c), a NAND gate 25 a second AND circuit (d), a NAND gate 26 a fourth AND circuit (f), an OR gate 27 a third OR circuit (g), an EOR gate 28 a first exclusive OR circuit (j), a NAND gate 29 a fifth AND circuit (h), an EOR gate 30 a second exclusive OR circuit (k), an AND gate 31 a sixth NAD circuit (l), a NOR gate 32 a fourth OR circuit (i) and a NOR gate 33 a fifth OR circuit (m). Thus, the critical path can be set to two NAND gates 22 and 23 and two EOR gates 28 and 30, and to be the delay of six unit delays.