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Test method for detecting faulty memory cells in a programmable semiconductor device

机译:用于检测可编程半导体器件中故障存储单元的测试方法

摘要

For testing unwritten-in field programmable memory cells, some specified written-in cells have been previously provided in the semiconductor device. In the first method, while a readout circuit, which reads datum written in the memory cell, is enabled, addressing-signals selecting the memory cell are switched from the written-in cell to a unwritten-in cell to be tested. Then, the voltage of the bit line operatively connected to the selected unwritten-in cell starts to rise gradually to that of the unwritten-in cell. The delay of this rising voltage, after the moment of the address-switching, is detected by the voltage level at a predetermined time, or by the time when this rising voltage reaches a predetermined threshold level. This delay corresponds to the degradation of the cell by leakage. In the second method, while the readout circuit is disabled, the addressing signals are switched from selecting written-in cell to selecting an unwritten-in cell to be tested, and then the readout circuit is enabled. The delay of the rising bit voltage is detected in the same way as those of the first method, but the time is measured from the moment at which the "enable" signal is applied. These delays can be also detected at the output terminal of the readout circuit.
机译:为了测试未写入的现场可编程存储单元,预先在半导体器件中提供了一些指定的写入单元。在第一种方法中,当启用了读取写入存储单元的数据的读出电路时,选择存储单元的寻址信号从写入单元切换到待测试的未写入单元。然后,可操作地连接到所选择的未写入单元的位线的电压开始逐渐升高至未写入单元的电压。在地址切换时刻之后,该上升电压的延迟通过预定时间的电压电平或该上升电压达到预定阈值电平的时间来检测。该延迟对应于电池由于泄漏而引起的退化。在第二种方法中,在禁用读出电路的同时,将寻址信号从选择写入单元切换为选择要测试的未写入单元,然后使能读出电路。以与第一种方法相同的方式检测上升位电压的延迟,但是从施加“启用”信号的那一刻起测量时间。这些延迟也可以在读出电路的输出端子处检测到。

著录项

  • 公开/公告号EP0214914B1

    专利类型

  • 公开/公告日1991-12-04

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号EP19860401968

  • 发明设计人 FUKUSHIMA TOSHITAKA;

    申请日1986-09-09

  • 分类号G11C29/00;

  • 国家 EP

  • 入库时间 2022-08-22 05:30:49

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