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Integration of high performance submicron CMOS and dual-poly non- volatile memory devices using a third polysilicon layer
Integration of high performance submicron CMOS and dual-poly non- volatile memory devices using a third polysilicon layer
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机译:使用第三多晶硅层集成高性能亚微米CMOS和双多晶硅非易失性存储设备
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摘要
An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.
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