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Method for characterizing the upset response of CMOS circuits using alpha- particle sensitive test circuits
Method for characterizing the upset response of CMOS circuits using alpha- particle sensitive test circuits
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机译:使用α粒子敏感测试电路表征CMOS电路翻转响应的方法
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摘要
A method for predicting the SEU susceptibility of a standard- cell D- latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.
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