Parallel processing circuit and a digital signal processer including same

摘要

A parallel processing circuit and a digital signal processor employing such a parallel circuit employs a plurality of identical multiply and accumulate (MAC) processing units. Two input signals are supplied to each of the MAC processing units. In one embodiment, a delay or a shift register delays one of the input digital signal from one MAC to another MAC. A plurality of different processed signals can be generated simultaneously based upon the supplied input digital signals, greatly increasing processing capability without increasing clock speed or increasing bandwidth access to a memory.