DESIGNING SCHEME FOR SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PURPOSE: To reduce a time required for development and a chip area by analyzing the first delay characteristic of an internal circuit, excluding an input/output buffer, subsequently, analyzing the second delay characteristic of a chip, including the input/output buffer, and then verifying whether characteristic requirements are met or not. CONSTITUTION: An internal block is laid out, and a first delay simulation is performed (101, 102). It is verified based on the result of the delay simulation whether there is no problem associated with characteristics (103). After a buffer allocating process, buffers in the internal block and a peripheral block are placed and wired, and the chip is finally laid out (104, 105). In addition a second delay simulation is performed, and final specifications are checked based on the result of the second delay simulation (106, 107). This accomplishes the reduction of the area of the chip and the time required for its development.