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teremetoride - ta compilation timing occurrence circuit

机译:特热么tori的 - 他compilation timing occurrence circuit

摘要

PURPOSE:To miniaturize the circuit by constituting a ROM of two stages, controlling the ROM of a post-stage by the ROM of a pre-stage, and switching an address of the ROM of a second stage by a multiplexer. CONSTITUTION:A control code for designating in advance a telemetry data editing port subjected to addressing by a part of output data of a first ROM 8, an address signal inputted from a multiplexer 7, and a part of a frame address inputted from an address bus 11 is stored in a second ROM 9. From a prescribed telemetry editing port designated by a second ROM 9, a timing signal is generated. By constituting the ROM of two stages, it will suffice that only the minimum necessary address information is stored in the ROM 9, and the redundancy can be eliminated. Also, by inserting the multiplexer 7 of the address between the ROM 8 and the ROM 9, compressibility of telemetry data can be set to variable length. In such a way, the number of pieces of ROMs to be used can be curtailed remarkably.
机译:目的:通过构成两级ROM,通过前级ROM控制后级ROM,以及通过多路复用器切换第二级ROM的地址来使电路小型化。组成:一个控制代码,用于预先指定遥测数据编辑端口,该端口要通过第一ROM 8的输出数据的一部分,从多路复用器7输入的地址信号以及从地址总线输入的一部分帧地址进行寻址将图11中所示的信号存储在第二ROM 9中。从第二ROM 9指定的指定遥测编辑端口,产生定时信号。通过构成两级的ROM,足以在ROM 9中仅存储最小必需的地址信息,并且可以消除冗余。另外,通过在ROM 8和ROM 9之间插入地址的多路复用器7,可以将遥测数据的可压缩性设置为可变长度。以这种方式,可以显着减少要使用的ROM的数量。

著录项

  • 公开/公告号JP2518098B2

    专利类型

  • 公开/公告日1996-07-24

    原文格式PDF

  • 申请/专利权人 NIPPON ELECTRIC CO;

    申请/专利号JP19900282241

  • 发明设计人 OOTSUKA MAKOTO;

    申请日1990-10-19

  • 分类号G08C15/06;H04Q9/00;

  • 国家 JP

  • 入库时间 2022-08-22 03:58:02

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