Efficient, high frequency, class A-B amplifier for translating low voltage clock signal levels to CMOS logic levels

摘要

A power efficient class A-B amplifier provides 20 dB amplification for a low capacitive load such as a 40 to 80 MHz clock signal in a crystal oscillator circuit. The amplifier includes two bias- and-clamp circuits coupled between an input stage and the gates of an N- channel transistor and a P-channel transistor. The N-channel and P- channel transistors are connected in series between VCC and ground and form an output stage. The bias-and-clamp circuits bias the N-channel and P-channel transistors in weak inversion for maximum amplification and clamp an input voltage to increase noise immunity and reduce power use. In one embodiment, each bias-and-clamp circuit includes two pairs of series connected transistors. A first pair is connected in series with a constant current source and form current mirrors with a second pair of transistors. A node between transistors in the second pair is connected to the gate of a transistor in the output stage and to the input voltage. Transistors in the bias-and- clamp circuits have a conductivity type which matches the conductivity type of the transistor in the output stage which the bias-and-clamp circuit controls.