首页> 外国专利> Method and apparatus for detecting synchronizing signals by latching successived count values that represent time between received sync pulses for comparison to a predetermined sync pattern of count values

Method and apparatus for detecting synchronizing signals by latching successived count values that represent time between received sync pulses for comparison to a predetermined sync pattern of count values

机译:通过锁存表示接收到的同步脉冲之间的时间的连续计数值以与计数值的预定同步模式进行比较来检测同步信号的方法和装置

摘要

A synchronization signal detector for detecting synchronization signals or frame synchronization signals recorded on a recording medium includes a binary-valued signal detector for translating RF signals into binary-valued signals, an edge detection circuit for extracting edge portions of the binary-valued signals, a counter for counting the number of clocks generated by an external source between the edge portions, a number of latch circuits for holding successive clock count values between the edge portions and for successively shifting the clock values held by them, value coincidence circuits for comparing the numbers of clocks between transitions of the synchronization patterns and the clock count values held by the counter and the latch circuits and for outputting a signal indicating a coincidence in case of complete coincidence between the numbers of clocks and the clock count values and an AND circuit for taking a logical sum of the outputs of the value coincidence circuits and the edge detector for producing a detection output of the synchronization signal. The synchronization signal may be detected efficiently with a short delay time and by a simple circuit construction even if the synchronization signal pattern is of a longer length. A demodulator utilizing the synchronization signal detector is also disclosed.
机译:一种用于检测记录在记录介质上的同步信号或帧同步信号的同步信号检测器,包括:用于将RF信号转换成二进制值的信号的二进制值的信号检测器;用于提取二进制值的信号的边缘部分的边缘检测电路;计数器,用于对边缘部分之间的外部源产生的时钟数进行计数;多个锁存电路,用于在边缘部分之间保持连续的时钟计数值,并用于连续移位它们所保持的时钟值;用于比较数字的值重合电路同步模式的转变之间的时钟和由计数器和锁存电路保持的时钟计数值之间的时钟,用于在时钟数和时钟计数值之间完全一致的情况下输出表示一致的信号,以及用于获取值符合电路的输出的逻辑和边缘检测器,用于产生同步信号的检测输出。即使同步信号图案具有较长的长度,也可以以短的延迟时间并且通过简单的电路构造来有效地检测同步信号。还公开了一种利用同步信号检测器的解调器。

著录项

  • 公开/公告号US5646966A

    专利类型

  • 公开/公告日1997-07-08

    原文格式PDF

  • 申请/专利权人 SONY CORPORATION;

    申请/专利号US19930084860

  • 发明设计人 YASUYUKI CHAKI;HIROYUKI INO;

    申请日1993-06-29

  • 分类号H04L7/00;

  • 国家 US

  • 入库时间 2022-08-22 03:09:49

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