PURPOSE: To shorten processing time by applying parallel processing to every two or more RUN/LEVEL sets. ;CONSTITUTION: A pointer 1 outputs data 0', 0', and RUNa=0 is supplied An adder 2 executes addition 0+0, and sends result data M'0' to a decoder 5. Simultaneously, RUNb=0 is supplied to an adder 3, and addition 0+0+1 (CY) is executed, and result data L'1' is sent to an adder 4, and data H'1' i.e., the result of addition 1+0 is sent to a decoder 6. The output of the decoders 5, 6 are inputted to the terminals D0, D1 of a selector 9 via latches L1, L2. The data M'0' and N'1' are also supplied to a selector 7, and the data N'1' is selected, and addition 1+1 (CY) is executed by an adder 8, and result data P's' is sent to the pointer 1. Similarly, addition processing is applied to third and fourth pairs of RIN/LEVELs. A logic circuit 10 supplies the output of the decoders 5, 6 to the terminals D4, D6 of the selector 9 via latches L4, L6.;COPYRIGHT: (C)1996,JPO
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