Partial integral being superimposed die reference frequency generation manner, and its reference frequency generation circuit null for phase lock looping

摘要

PURPOSE:To generate a reference frequency for a partial integration superimposing type phase locked loop in which the frequency is compensated with high precision at a low cost in the generation of the reference frequency signal driving the phase locked loop. CONSTITUTION:The method is provided with accumulation means 201,202 calculating a digital setting value fed from a phase increment setting section 203 synchronously with a prescribed clock, one-period integration period detection means 104-106 for top, bottom region and original integration region of a period integration period detection means 204-206, partial integration compensation generating means 208, 209 corresponding to each section, D/A converter means 215, 218, a signal changeover means 216 selecting an analog signal from the D/A converter means 216, integration means 221, 222 superimposingly inputting the signal from the means 216 and the analog signal from the D/A converter means 218 and a comparator 225 connecting to the post-stage.