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Insulating by the on the substrate of the n-type semiconductor material, at the same time the manner null which forms the integrated circuit which possesses PNP and the NPN transistor which possess the flow of electric current of the vertical
Insulating by the on the substrate of the n-type semiconductor material, at the same time the manner null which forms the integrated circuit which possesses PNP and the NPN transistor which possess the flow of electric current of the vertical
In this process P+ type regions are diffused on a substrate of N type semiconductor material, said regions forming the horizontal isolation region of the NPN transistors and the low-resistivity collector region of the PNP transistors. Within each isolation region a high-concentration N+ type zone is created that acts as a low-resistivity collector region for the NPN transistors. An N type epitaxial layer is then grown over the whole surface of the device. The completion of the device is carried out in such a way to ensure that the low-concentration collector thickness of transistors NPN be practically equal to the low-concentration collector thickness of transistors PNP.
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