Selective History CRC-32 Processing Encoders and Decoders and Their Parallel Processing Method

摘要

The present invention relates to an optional parallel CRC-32 processing encoder, a decoder and a parallel processing method. The purpose is to enable the CRC-32 to be selectively parallelized in 8-bit, 16-bit, and 32-bit units according to mode selection. The 32-bit temporary storage unit updates the value of each clock and outputs the value. The input data and the output of the 32-bit temporary storage unit are input to the encoder, And a remaining calculation unit for updating the stored value of the 32-bit temporary storage unit every clock. A multiplexing unit for multiplying the input data and the calculated CRC-32 value, and a control unit for generating and supplying signals necessary for each block. A 32-bit temporary storage unit for updating the value of each clock and outputting the updated value, an input unit for receiving input data and an output of the 32-bit temporary storage unit, A syndrome comparison unit for comparing CRC-32 calculated values for the received syndrome value with the predicted syndrome value for no error, and a syndrome comparison unit for comparing the calculated syndrome value with the CRC-32 calculated value for the received data, A controller for generating and supplying a buffer part used for timing control to obtain error information of the data and error information of the data for which the CRC-32 field is removed, and supplying necessary signals to each block, and an optional parallel CRC-32 processing decoder .