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Method of power reduction in pla's

机译:中国人民解放军降低功率的方法

摘要

A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull- up devices is minimized.
机译:公开了一种降低功率的可编程逻辑阵列。该电路包括通过乘积项线耦合到输出或阵列的与阵列。 OR阵列中的上拉器件被选通到有效乘积项线之一。还公开了用于选择用于对上拉器件进行门控的乘积项线以使上拉器件中的功耗最小化的方法。

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