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METHOD AND DEVICE FOR OPTIMIZING SIGNAL LINE IN CIRCUIT AND STORAGE MEDIUM FOR STORING OPTIMIZATION PROGRAM OF SIGNAL LINE IN CIRCUIT

机译:用于电路中的信号线的优化的方法和装置以及用于存储电路中的信号线的优化程序的存储介质

摘要

PROBLEM TO BE SOLVED: To design a circuit that can cope with the request for a high speed by optimizing the delay in a signal from a signal supply source to each element for positively reducing the skew. ;SOLUTION: When a signal is to be directly supplied to all of a plurality of elements where a signal supply source is an element to be driven, a judgment part 41 for judging whether a fan-out restriction is satisfied, a division part 43 for dividing the element to be driven into a plurality of groups so that the fan-out restriction can be satisfied and the number of elements and a load capacity are equal or nearly equal, and a buffer insertion part 44 for inserting buffer elements with a size for satisfying the fan-out restriction for each divided group are provided. As a result, a buffer element where the judgment part 41 is inserted is treated as an element to be driven for judging to see if the signal supply source satisfies the fan-out restriction or not, and a processing by the division part 43 and the buffer insertion part 44 is repeated until it is judged that the fan-out restriction can be satisfied.;COPYRIGHT: (C)1999,JPO
机译:要解决的问题:设计一种电路,通过优化从信号供应源到每个元件的信号延迟来积极减少偏斜,从而设计出可以应对高速需求的电路。 ;解决方案:当信号要直接提供给信号驱动源是要驱动的多个元件的所有元件时,用于判断是否满足扇出限制的判断部分41,将要驱动的元件分成多个组,以便可以满足扇出限制,并且元件的数量和负载容量等于或接近相等,并且缓冲器插入部分44用于插入具有用于提供满足每个划分组的扇出限制的条件。结果,插入判断部41的缓冲元件被当作要被驱动的元件,以判断信号供给源是否满足扇出限制,并且由划分部43和处理部进行处理。重复缓冲器插入部分44,直到判断出可以满足扇出限制为止。;版权:(C)1999,JPO

著录项

  • 公开/公告号JPH11214517A

    专利类型

  • 公开/公告日1999-08-06

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19980012545

  • 发明设计人 SUGIOKA TOSHIAKI;SANO MASAHIRO;

    申请日1998-01-26

  • 分类号H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-22 02:34:33

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