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Method of analyzing logic circuit test points, apparatus for analyzing logic circuit test points and semiconductor integrated circuit with test points

机译:分析逻辑电路测试点的方法,分析逻辑电路测试点的设备以及具有测试点的半导体集成电路

摘要

A test point analyzing apparatus performs distinction between capability and incapability of insertion of a test point and a circuit modifying way when a test point is capable of being inserted for each of the test point types to each of the signal lines in a semiconductor integrated circuit by using circuit information (122), a test point insertion library (123) specifying sets of a test point type capable of being inserted and a circuit modifying way, and test point insertion prohibiting information (124) specifying sets of a signal line and a test point type for which it is prohibited to insert a test point. Then, test point indexes to test point candidates capable of being inserted are calculated, and test point candidates having a large testability are selected based on the indexes, and the selected test point candidates are registered in test point information (127). The above-mentioned processing is repeated until a predetermined condition of completing the test point analysis process. Furthermore, in the apparatus, a test point index calculation portion (112) calculates test point index information (126) including CRF (Cost Reduction Factor ) of each signal line from circuit information, determines a predetermined number of test point candidates in order of the CRF, and calculates COP (Controllability Observability Procedure, hereinafter referred to as test cost) when each of the test point candidates is assumed to be inserted. By setting candidates of the minimum COP as test points, a test point determining portion (113) searches the other test point candidates not intersecting with an effect region of the test points in increasing order, and if there exists a test point candidate not intersecting with an effect region, the test point is added to a new test point group.
机译:当能够针对半导体集成电路中的每条信号线将每种测试点类型的测试点插入到半导体集成电路中的每条信号线上时,测试点分析装置进行测试点插入的能力与能力之间的区别以及电路修改方式。使用电路信息(122),指定能够插入的测试点类型的集合的测试点插入库(123)和电路修改方式,以及指定信号线和测试的集合的测试点插入禁止信息(124)禁止插入测试点的点类型。然后,计算针对能够插入的测试点候选的测试点索引,并且基于该索引选择具有大的可测试性的测试点候选,并且将所选择的测试点候选注册在测试点信息中(127)。重复上述处理,直到完成测试点分析处理的预定条件为止。此外,在该装置中,测试点指标计算部分(112)从电路信息计算包括每条信号线的CRF(成本降低因子)的测试点指标信息(126),并按照以下顺序确定预定数量的测试点候选者: CRF,并在假定插入每个测试点候选时计算COP(可控性可观察性程序,以下称为测试成本)。通过将最小COP的候选设置为测试点,测试点确定部分(113)以递增的顺序搜索不与测试点的效果区域相交的其他测试点候选,并且是否存在不与测试点相交的测试点候选。在效果区域中,将测试点添加到新的测试点组中。

著录项

  • 公开/公告号EP0852353A3

    专利类型

  • 公开/公告日1999-04-07

    原文格式PDF

  • 申请/专利权人 HITACHI LTD.;

    申请/专利号EP19980300029

  • 申请日1998-01-06

  • 分类号G06F11/263;G06F11/267;G01R31/3185;

  • 国家 EP

  • 入库时间 2022-08-22 02:19:44

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