首页> 外国专利> MULTIPLEX CELL-DISASSEMBLING PROCESSOR AND MULTIPLEX CELL-DISASSEMBLING METHOD

MULTIPLEX CELL-DISASSEMBLING PROCESSOR AND MULTIPLEX CELL-DISASSEMBLING METHOD

机译:多重细胞二元分解处理器和多重细胞二元分解方法

摘要

PROBLEM TO BE SOLVED: To provide a multiplex cell-disassembling processor with which a buffer capacity and quantity of buffer management information can be reduced and a cell-disassembling time can be decreased. ;SOLUTION: A header/payload separation processing section 11 separates a header part and a payload data part of an ATM cell. A loss error-in delivery processing section 12 conducts cell loss error in delivery detection, cell compensation at detection of cell loss, and cell abort at detection of cell error-in delivery. A common buffer section 14 stores in advance the pattern of a dummy cell and has banks in units of cells storing the payload part of the received ATM cell. A CAM section 16 stores data correlating an ATM/AAL header with an address where the payload is stored. A complementary FIFO section 17 stores data correlating the cell loss number detected by the loss error-in delivery processing section 12, the ATM header and the AAL header with the addresses in which the payload is stored.;COPYRIGHT: (C)2000,JPO
机译:解决的问题:提供一种多路复用单元分解处理器,利用该处理器可以减少缓冲器容量和缓冲器管理信息量,并且可以减少单元分解时间。 ;解决方案:标题/有效载荷分离处理部分11分离ATM信元的标题部分和有效载荷数据部分。送入错误输入处理部12进行送出检测中的单元丢失错​​误,检测到单元丢失时的单元补偿,以及检测到单元错误输入时的单元中止。公用缓冲器部分14预先存储伪信元的模式,并具有以信元为单位存储存储所接收的ATM信元的有效载荷部分的存储体。 CAM部分16存储使ATM / AAL报头与存储有效载荷的地址相关的数据。互补FIFO部分17存储与丢失丢失输入处理部分12检测到的信元丢失数目,ATM头和AAL头以及存储有效载荷的地址相关的数据。版权:(C)2000,JPO

著录项

  • 公开/公告号JP2000216793A

    专利类型

  • 公开/公告日2000-08-04

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP19990017878

  • 发明设计人 SOEDA YASUYUKI;

    申请日1999-01-27

  • 分类号H04L12/28;H04Q3/00;

  • 国家 JP

  • 入库时间 2022-08-22 01:59:08

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