INTEGRATED HARDWARE AND SOFTWARE TASK CONTROL EXECUTIVE

摘要

A method and system for permitting a software-based executive to execute concurrently with a hardware-based executive (161). The software-based executive (166) allocates hardware executive tasks, hardware executive interrupts, software executive tasks, and software executive interrupts to defined execution spaces available on a microprocessor having a hardware-based executive (161). Applications control hardware-based executive tasks and interrupts through a hardware executive application programming interface (API, 170), and software-based executive tasks through a software executive (API, 167). Applications share the hardware executive API (170) functions for interrupt installation and management. The invention allocates all hardware executive interrupts (165) to a high priority interrupt execution space, and all hardware executive tasks to a high priority queue. All software executive interrupts are allocated to low priority interrupts. The software executive uses a special context switch mechanism (188) that changes the currently executing task without creating another low priority task. In this way, the low priority hardware scheduler (186) is always disabled, and low priority tasks are always under the control of the software executive. A hierarchical "enables" mechanism protects critical sections of code during reentrances. An interrupt return revectoring mechanism is provided to provide a mechanism for preemption. When a software executive interrupt occurs, the interrupt return revectoring mechanism (189) exits the interrupt and revectors into the software kernel so that a new kernel task can begin executing, rather than returning to the previously executing task. A mechanism is also provided to accommodate block move operations.