The synchronous counter for high cycle rates

摘要

The counter has toggle stages and gates. At least the higher value counter toggle stages (CL) apart from the highest value stage each have an associated additional memory toggle stage. The inputs of the higher value counter toggle stages are each connected to a logic circuit. The output signal of the previous lower value counter toggle stage and its associated memory stage are fed to the logic circuit. Preferably the toggle stages are D type flip flops. Alternatively the counter toggle stages may be a JK flip flops. The logic circuit may be an AND gate which outputs a logic signal.