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Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash
Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash
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机译:制造掩埋源以缩小单元尺寸并增加分裂栅闪速中耦合比的方法
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摘要
A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.
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