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Clock circuit employable for sequential regulation systems having multiple functions

机译:可用于具有多种功能的顺序调节系统的时钟电路

摘要

A clock pulse circuit having a construction of multiple stories provided with a terminal for a clock pulse generator, a first story trunk line connected the clock pulse generator, a plurality of first story branch lines, each of which is connected the first story trunk line, a plurality of second story trunk lines each of which is connected one of the second story trunk liens, a plurality of second story branch lines, each of which is connected one of the second story trunk lines, and PPa plurality of combinations of higher story trunk lines and higher story branch lines, such combinations being composed of in the similar manner as is defined above, wherein a switching element is provided between selected one of the branch lines and the trunk line following the selected one of the branch lines.
机译:一种具有多层结构的时钟脉冲电路,其具有用于时钟脉冲发生器的端子,第一层主干线连接时钟脉冲发生器,多条第一层主干线,每条第一层主干线连接到第一层主干线,多个第二故事主干线,每个第二主干线与第二故事主干线之一连接;多个第二故事主干线,每个第二主干线与第二故事主干线之一连接;以及

高层主干线和高层主干线的组合,这种组合以与上述定义类似的方式组成,其中,在所选的一条分支线和紧随其后的一条的主干线之间提供了一个开关元件分支线。

著录项

  • 公开/公告号US6034559A

    专利类型

  • 公开/公告日2000-03-07

    原文格式PDF

  • 申请/专利权人 OKI ELECTRIC INDUSTRY CO. LTD.;

    申请/专利号US19980038237

  • 发明设计人 HIROHISA MASUDA;

    申请日1998-03-11

  • 分类号H03K3/00;G06F1/04;

  • 国家 US

  • 入库时间 2022-08-22 01:37:38

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