Clock control circuit for generating an internal clock signal with one or more external clock cycles being blocked out and a synchronous flash memory device using the same

摘要

A clock control circuit receives an external clock signal and generates an internal clock signal. Through use of internal programming and an external trigger signal, the clock control circuit blocks out one or more of the clock cycles of the external clock signal to generate the internal clock signal. The clock control circuit can be used in any semiconductor device, and especially in synchronous flash memory devices with a burst operation. In the synchronous flash memory devices, one or more of the internal clock cycles are blocked out to account for increased delays during certain data sensing operations such as word line switching during data reading. In the synchronous flash memory devices, the sensed data is stored in input/output buffers and transferred out synchronously to the external clock signal.