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Logical cache memory storing logical and physical address information for resolving synonym problems

机译:逻辑高速缓存存储逻辑和物理地址信息,用于解决同义词问题

摘要

Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area is accessed, the physical page information PA (a) retained in the cache memory is compared with physical page information PA (b) resulting from the translation of a search address by TLB. When the result of the comparison is proved to be conformity, the cache entry is processes as a cache hit, so that the problem of a synonym arising from a case where the same physical address is assigned to different logical addresses is solved in such a manner that the number of times access is provided to TLB is halved as compared with the conventional arrangement.
机译:与作为高速缓存标签地址的逻辑页面信息VA(a)相对应的物理页面信息PA(a)被保留在逻辑高速缓存存储器10中,并且如果在访问共享区域时发生高速缓存未命中,则物理页面信息PA(将a)保留在缓存中的数据与物理页面信息PA(b)进行比较,该物理页面信息PA(b)是由TLB转换搜索地址得出的。当比较的结果被证明是合格的时,高速缓存条目被作为高速缓存命中进行处理,从而以这种方式解决了由于将相同的物理地址分配给不同的逻辑地址的情况而引起的同义词问题。与传统布置相比,提供给TLB的访问次数减少了一半。

著录项

  • 公开/公告号US6138226A

    专利类型

  • 公开/公告日2000-10-24

    原文格式PDF

  • 申请/专利权人 HITACHI LTD.;

    申请/专利号US19990359931

  • 发明设计人 SHINICHI YOSHIOKA;SHUMPEI KAWASAKI;

    申请日1999-07-22

  • 分类号G06F12/10;

  • 国家 US

  • 入库时间 2022-08-22 01:35:50

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