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The circuit which decides non homogeneous secondary far texture mapping coordinate making use of linear interpolation

机译:利用线性插值确定非齐次二次远纹理映射坐标的电路

摘要

(57) Abstract The texture value decisive (TVD) circuit, non homogeneous secondary far texture mapping closely resembling, offers texture to the polygon making use of linear interpolation and entry parameter. The TVD circuit of this invention, includes with the vertical walk sub circuit and the orthogonal walk sub circuit. The vertical walk sub circuit, the texture coordinate u (a0, n) which displays the pixel which parallels on principal inclination of the vertical of triangle and decides v (a0, n). The orthogonal walk sub circuit is m0, crossing, texture coordinate concerning the polygonal coordinate position which advances u (a m, n) and it decides v (a m, n). Crossing, the coordinate position which advances displays the individual scanning line. The vertical walk sub circuit of the TVD circuit, includes the adder, latch, and the accumulator. Each element of the vertical walk sub circuit receives the vertical main inclined clock (n clock) signal. Output of vertical walk subsystem is calculated something related to below, namely, concerning m=0 and n0, u (a0, n) =u (a0, n-1) +du on the basis of main+ (n1) d2 u main. Here, du main and d2 u main are entry parameter. In addition as for the orthogonal walk sub circuit, the adder, latch, and the accumulator are included. The orthogonal walk sub circuit the clock is done by the orthogonal walk (m clock) signal and the n clock pulse. Output of the orthogonal walk sub circuit is calculated something related to below, namely, concerning m0, u (a m, n) =u (a m-1 and n) +n (du ortho-ADD) +du on the basis of orthof (m1) d2 u ortho. Here, du ortho-ADD and du ortho and d2 u ortho are entry parameter.
机译:(57)<摘要>纹理值决定(TVD)电路,非常相似的非均匀次远纹理映射,利用线性插值和输入参数为多边形提供纹理。本发明的TVD电路包括垂直步进子电路和正交步进子电路。垂直行走子电路,纹理坐标u(a 0,n )显示与三角形垂直方向的主倾角平行并确定v(a 0,n )。正交步子电路为m> 0,与涉及使u(a m,n )前进的多边形坐标位置的纹理坐标相交,并确定v(a m,n ) >)。交叉时,前进的坐标位置显示单个扫描线。 TVD电路的垂直步进子电路包括加法器,锁存器和累加器。垂直行走子电路的每个元件都接收垂直主倾斜时钟(n时钟)信号。垂直行走子系统的输出的计算与以下内容有关,即涉及m = 0和n> 0,u(a 0,n )= u(a 0,n-1 < / Sub>)+ du基于 main + (n1)d 2 u main 。这里,du main 和d 2 u main 是输入参数。另外,对于正交步进子电路,包括加法器,锁存器和累加器。正交步进子电路的时钟由正交步进(m时钟)信号和n个时钟脉冲完成。正交行走子电路的输出计算如下:m> 0,u(a m,n )= u(a m-1和n )+ n(du ortho-ADD )+ du基于 orthof (m1)d 2 u ortho 。这里,du ortho-ADD 和du ortho 和d 2 u ortho 是输入参数。

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