首页> 外国专利> Method and apparatus for processing Data for multiplying a by multiplying by a multiplier of 2 bits, and the Data Processing method and apparatus for multiplying a by multiplying by multiplR - M digits

Method and apparatus for processing Data for multiplying a by multiplying by a multiplier of 2 bits, and the Data Processing method and apparatus for multiplying a by multiplying by multiplR - M digits

机译:用于通过乘以2位的乘数来乘以a的数据的处理方法和装置,以及用于通过乘以multiplR-M位来乘以a的数据处理方法和装置

摘要

Bit serial processors are quickly multiplications with multi bit operands using significantly less compared with the deciclos Watch implementsIn conventional serial bit. Such forms of realization of Process groups bitsdel operate simultaneously to provide significant increases in Speed.However, as appropriate, ways of realization deejemplo used Logic and Memory Architectures that are fully compatible with, and fully useful,Applications of bitsconvencionales serial and, this way,The embodiments allow Rapid multiplication with multiple bits at the same time provide the advantage that, in general,Are associated with the conventional bit serial Processors.
机译:与传统串行位中的Deciclos Watch工具相比,位串行处理器可快速使用多个位操作数进行乘法运算。进程组bitdel的这种实现形式可以同时运行,以显着提高速度。但是,在适当的情况下,实现的方式可以简化使用与bitconventionalionales串行应用完全兼容并完全有用的逻辑和内存体系结构,实施例允许与多个位同时快速相乘提供了通常与传统的位串行处理器相关联的优点。

著录项

  • 公开/公告号AR014837A1

    专利类型

  • 公开/公告日2001-03-28

    原文格式PDF

  • 申请/专利权人 LOCKHEED MARTIN CORPORATION;

    申请/专利号AR1999P101645

  • 发明设计人

    申请日1999-04-09

  • 分类号G06F9/00;

  • 国家 AR

  • 入库时间 2022-08-22 01:26:21

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