首页> 外国专利> De-channel allocating apparatus and method for non-eye service in wireless subscriber network system

De-channel allocating apparatus and method for non-eye service in wireless subscriber network system

机译:无线用户网络系统中用于非眼服务的解信道分配装置和方法

摘要

The present invention allows the WLL system to satisfy the WLL radio access standard while allocating D-channel to the minimum channel when connecting to the V5.2 and the BRI junction of the WLL switch, and modularizing the mounting board for system maintenance and The present invention relates to a device for allocating a channel to a minimum channel for a non-eye service in a wireless subscriber network system for easy scalability, and to converting an analog signal (A) input from the RFU (1) into a digital signal (D). A / D and D / A signal converters (2) and (3), which convert the digital data received from the modem into analog data to the RFU (1), and the signal converter (2) (3). D-channel in the data coming out through the first and second modem unit (4) (5) and the first and second modem unit (4) (5) for code division conversion of the data input from To find and collect these four into one 64Kbps channel CPU (7) and the CPU (7) which frame the data received from the channel handler / HDLC controller (6), the channel handler / HDLC controller (6) to perform IPC communication and controls the entire block A memory (8) connected to the memory (8) for temporarily storing variables or data, an IPC interface (9) connected between the CPU (7) and the main processor (12) to perform IPC communication, and the first and second It consists of mux / demux 10 which makes 64Kbps data output through 2 modem (4) (5) to 2.048bps.
机译:本发明允许WLL系统满足WLL无线电接入标准,同时在连接到WLL交换机的V5.2和BRI结时将D信道分配到最小信道,并且模块化安装板以进行系统维护。 [0001]本发明涉及一种设备,该设备用于在无线用户网络系统中为无眼服务的最小信道分配信道以便于容易扩展,并且涉及将从RFU(1)输入的模拟信号(A)转换为数字信号( D)。 A / D和D / A信号转换器(2)和(3),它们将从调制解调器接收到的数字数据转换为模拟数据,再传输到RFU(1),以及信号转换器(2)(3)。通过第一和第二调制解调器单元(4)(5)以及第一和第二调制解调器单元(4)(5)出来的数据中的D通道,用于对从中输入的数据进行码分转换,以查找并收集这四个信号一个64Kbps通道CPU(7)和CPU(7),它们对从通道处理程序/ HDLC控制器(6),通道处理程序/ HDLC控制器(6)接收的数据进行帧处理以执行IPC通信并控制整个块A存储器( 8)连接到用于临时存储变量或数据的存储器(8),IPC接口(9)连接在CPU(7)和主处理器(12)之间以执行IPC通信,第一和第二个由多路复用器组成/ demux 10,使通过2个调制解调器(4)(5)输出的64Kbps数据达到2.048bps。

著录项

  • 公开/公告号KR100282801B1

    专利类型

  • 公开/公告日2001-03-02

    原文格式PDF

  • 申请/专利权人 현대전자산업주식회사;

    申请/专利号KR19980049939

  • 发明设计人 지창환;

    申请日1998-11-20

  • 分类号H04B7/26;

  • 国家 KR

  • 入库时间 2022-08-22 01:12:30

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号