MASK PATTERN VERIFICATION APPARATUS EMPLOYING SUPER-RESOLUTION TECHNIQUE MASK PATTERN VERIFICATION METHOD EMPLOYING SUPER-RESOLUTION TECHNIQUE AND MEDIUM WITH PROGRAM THEREOF

摘要

The mask pattern verifying apparatus includes a semiconductor circuit layout section for generating layout data from semiconductor circuit data, and a super resolution for verifying a pattern of layout data generated by the semiconductor circuit layout section on the basis of the pitch plus the line width and the space width. The cantour is based on the corresponding pattern verification unit, the optical simulation unit for performing optical simulation of the error point of the pitch detected by the super-resolution pattern verification unit, and outputting the light intensity, and the light intensity output by the optical simulation unit. It includes a cantour output unit for generating and outputting.